Crocus’ Magnetic Logic Unit™ (MLU) architecture is based on its patented, revolutionary self-reference technology using Thermally Assisted Switching™ (TAS) and Differential Thermally Assisted Programming (DTAP). Self-reference TAS (SR-TAS) enables a number of previously unachievable breakthroughs in magnetic technology implementation, including ultra-sensitive magnetic sensors, highly robust secure embedded memory, ultra-high-temperature non-volatile memory (NVM) operation (e.g., ~200° C), order-of-magnitude higher density hardware-based table searches (e.g., content addressable memory), high density multi-bit storage, and scaling to sub-20nm manufacturing. The DTAP technology enables unique differential programming of sensors devices that leads to improved performance.
The MLU technology has been developed as a platform technology that serves as a base for multiple products, from magnetic sensors, to memories, to security products. At the heart of the MLU technology, there is a thin film magnetoresistive device, the so-called Magnetic Tunnel Junction (MTJ). In its simplest form the MTJ consists of two magnetic layers sandwiching a thin insulating layer. The electrical resistance of the MTJ depends on the angle between the magnetic moments of each layer being high with anti-parallel and low when parallel. There are some variations in the MTJ device structure depending on the type of the product.
MLU Technology for Sensor Products
Crocus magnetic field sensors use a simple form of the MTJ. In this case the MTJ device consists of two magnetic layers as shown in Fig. 1. One of the two magnetic layers has its magnetic orientation pinned using an antiferromagnetic layer below and it is called a reference layer. The other magnetic layer, called a sensing layer, is free to change its orientation in the presence of an external magnetic field. The reference layer is typically programmed during manufacturing by using Crocus’ patented DTAP technology.
The resistance of the MTJ depends on the angle between the magneticmoments of the sense and reference layer. Since the external field influences the sensing layer orientation, the MTJ resistance depends on the external magnetic field. When the magnetic field is antiparallel to the reference layer the MTJ shows high resistance, while when it is parallel to the reference layer, the MTJ shows low resistance. External magnetic field will determine which one of the two will prevail. The functional curve of the basic MTJ is shown in Fig. 2. One can clearly distinguish three regions on the curve: High resistance region (reference and sense layer are in antiparallel), transition region (resistance of MTJ changes from high to low resistance), and saturation region with low resistance (reference and sense layer are in parallel). The middle of the transition region is typically used for linear application where direct correlation between the resistance and intensity and direction of magnetic field can be established.
The actual sensor device is designed by using a large number of MTJs arranged in an array as shown in Fig. 3. Not only does this give and inherently robust device, this gives great flexibility in creating output resistances of magnetoresistor from several ohms to a hundred kohms which is very useful to target different applications. Additionally such sensor devices can be directly power with relatively large voltages.
Crocus has introduced multiple innovations around this basic principle in order to develop a family of magnetic field sensors.
MLU Technology for Memory Products
The basic MRAM cell is also composed of a MTJ which consists of two magnetic layers sandwiching a thin insulating layer as shown in Fig.4. Here too one layer serves as a reference layer, while the other layer acts as the storage layer and it can be switched either parallel or antiparallel to the reference layer giving either a low or high resistance respectively. The corresponding logic state ("0" or "1") of the memory is hence defined by its resistance state (low or high), monitored by a small read current. It should be pointed out that memory does not use transition region for operation but it rather makes use of either uses high or low resistance mode.
In traditional MRAM architectures, memory cells consisting of a CMOS selection transistor and a magnetic tunnel junction are put into a 2D array. Each memory cell can be addressed individually with each MTJ being in a cross point architecture with control field lines. This technology has been used efficiently in the first generation of MRAM devices, developed so far with feature sizes greater than 0.13-0.18 µm.
However such an approach has limited scalability and going to smaller technology nodes requires a different architecture. Crocus and its partner research centres SPINTEC and LETI developed and demonstrated within the IST European program "NEXT" a unique technology called “TAS” (Thermally Assisted Switching) protected by a broad IP portfolio. The key feature was to add an antiferromagnetic layer to the storage layer of the MTJ thereby pinning the stored information and allowing it only to be re-written by local Joule heating of the MTJ. The Crocus MRAM technology not only allows full scalability to technology nodes at 90nm and below, but also exhibits high speed, error-free addressing, reduced power consumption and radiation/magnetic field hardness.
Crocus Magnetic Logic Unit
In addition to TAS-RAM, Crocus has developed a new concept named Self-Reference (SR) which is at the heart of Magnetic Logic Unit (MLU) architecture. SR goes much further in resolving additional challenges and enabling new functionalities and capabilities.
The key feature of the SR MTJ is that it does not require a fixed reference layer. This is achieved by removing the antiferromagnetic layer that pins the reference. As a result, the magnetization of this layer is free to vary and is renamed as the sense layer.
The SR memory cell operates differently from the fixed reference (FR)-TAS memory cell as shown in Fig.5. The mechanism of writing data into the memory cell in SR and FR configurations is identical: A small current flows through the MTJ and heats the cell to the critical write temperature while concurrently applying a magnetic field to orient the storage layer. Then, the MTJ is cooled while write field is maintained, essentially "freezing" the magnetic state into the storage layer. The orientation of the sense layer is irrelevant during write operation. Crocus has optimized the heating current by including a proprietary thermal barrier inside and around the MTJ to maximize the incremental temperature.
However, the read mechanism in the FR and SR configuration is quite different.
In the SR case, read is achieved by measuring the MTJ resistance twice as shown in Fig 6. The first measurement is performed with the sense layer aligned in one direction and the second measurement in the opposite direction. The alternate alignment of the sense layer is achieved by first driving a "north" current in the corresponding filed line followed immediately by a "south" current, which can be achieved in a 5 to 10ns time lapse. The magnitude of the field line current required to align the sense layer is roughly equal to field line current required to write sequence. But the power applied to the MTJ during read sequence is approximately one tenth of the power applied during write sequence. As a consequence, there is no risk of unwanted write due to self-heating during read.
The SR read not only enables a very robust memory cell but also allows it to be used as a true logic element. Direction of the current flowing in the field line can be used as an information input. The resistance of the cell now compares the stored information and the input information — if sense and storage layers are aligned in parallel the resistance is low and if sense and storage layers are anti-parallel the resistance is high. The element acts as an XOR (exclusive OR) logic device whose output depends on the comparison of the stored information and an input information (via the field line).
Crocus Magnetic Logic Unit architecture for Match In Place
Starting from MLU concept, Crocus has developed an innovative function called Match-In-Place, to authenticate users without exposing any confidential data to a security attacker. Expected advantages are:
• The sensitive stored data are never read and exposed to attacker,
• The matching cycles can be orders of magnitude more efficient than existing solution in term of speed and power,
• Match In Place engines could act as a hardware accelerator, simplify the IC architecture and reduce its overall price.
Each cell of the Match-In-Place architecture is a non-volatile memory cell combined with the virtual XOR gate of the MLU. Multiple cells are connected in series to form a NAND chain acting as a linear Match-In-Place engine. If multiple Match-In-Place NAND chains are placed in parallel, they can act in the same time to compare one pattern against many.
In Fig.7 a set of 4 MLU cells are connected serially and form a NAND chain that create a linear Match-In-Place engine. The input binary pattern 0011 is compared to the stored binary pattern 1010. Each stored bit is individually compared to the bit of the same rank. The MTJ being physically linked together, the resulting resistor is compared to the reference, enabling decision of match or un-match between the 2 words.
Fields of use of this new architecture are quite wide and include secure microcontrollers, biometric devices and associative memory devices.